Application of Silica Sol in Chip Polishing
Release date:
2026-02-13
Silica sol can serve as a key ingredient in CPM polishing liquids because it is a dispersion of nanoscale silica particles. These nanoparticles exhibit excellent sphericity, and the hardness of the silica sol particles is appropriately balanced, which can significantly reduce scratches on devices during the polishing process.
In the mid-1960s, most semiconductor substrate polishing still relied on mechanical polishing, which resulted in extremely severe surface damage on the polished mirror-like surfaces. Starting in the 1970s, chemical-mechanical polishing (CMP) technology—represented by silica sol—gradually replaced traditional mechanical polishing. Since the 1990s, with the rapid development of the electronics industry, demand for silica sol, as a key raw material for silicon wafer polishing fluids, has surged dramatically. The so-called polishing agent consists of silica sol, water, dispersing and stabilizing agents, wetting regulators, pH adjusters, and surface treatment agents. Silica sol is an excellent polishing material widely used in CMP technology; it can be applied to both coarse and fine polishing of silicon wafers as well as in IC fabrication processes. It is particularly well-suited for planarization of multilayer films in large-scale integrated circuits. Moreover, silica sol can also be used in post-CMP cleaning of wafers and other processing steps involved in the manufacture of semiconductor devices, flat-panel displays, polycrystalline modules, micro-electromechanical systems, and photoconductive image tubes.
Silica sol The reason silicon sol can serve as a key ingredient in CPM polishing liquids is that it is a dispersion of nano-sized silica particles with excellent sphericity and an appropriately controlled hardness. This helps significantly reduce scratches on devices during the polishing process. According to current manufacturing technologies, the diameter of the nano-silica particles in silicon sol can be precisely controlled within the range of 10 to 150 nm. Different particle sizes of silicon sol result in varying removal rates, providing numerous options for the planarization processes used in chip manufacturing. As a result, silicon sol has become the preferred raw material for CMP polishing liquids currently used in chip fabrication.
C PM Schematic diagram of the polishing process
CMP stands for Chemical Mechanical Polishing, or chemical-mechanical polishing. The chip manufacturing process is akin to building a house: each time a new floor is constructed, it must be perfectly level and evenly aligned before the next floor can be built on top. Otherwise, the floors would end up uneven, compromising the overall reliability of the structure. The technology used in chip manufacturing to ensure that each floor is uniformly flat is precisely chemical-mechanical polishing.
CMP is a process technology that combines the physical abrasion action of nanoscale particles with the chemical etching effect of polishing liquids to achieve planarization and ultra-high surface flatness on chip devices. Currently, in chip manufacturing, the CMP process is primarily used to precisely polish wafer surfaces, enabling global flatness tolerances as low as 100 Å to 1,000 Å (equivalent to 10 to 100 nm at the atomic level).
CMP is primarily used for polishing single-crystal silicon wafers and for interlayer planarization in multilayer wiring metal interconnect processes. Integrated circuit manufacturing involves a series of physical and chemical operations performed on single-crystal silicon wafers. As device feature sizes continue to shrink, the number of production steps required increases accordingly—processes below 90 nm typically involve more than 400 fabrication steps. In terms of polishing processes, different product generations require distinct polishing sequences: the 28-nm process requires 12 to 13 CMP steps, while once the process reaches 10 nm, the number of CMP steps doubles, rising to between 25 and 30 steps.
Therefore Silica sol As a nano-silica dispersion with controllable particle size, it plays a critical role in CMP polishing slurries.
The CMP polishing slurry used in chip manufacturing has stringent requirements for silica sol. In addition to strict control over particle size, it also imposes extremely high purity standards, demanding that the content of metallic impurities be kept below 1 ppm. This is because current chip manufacturing technology has reached a precision level as fine as 5 nm. If the silica sol contains metallic ion impurities such as sodium, potassium, and iron, these impurities can contaminate the microcircuits on the chip, leading to breakdown and damage during operation. Therefore, the silica sol used in chip polishing slurries must have a metal ion content controlled at the ppb level.
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